Work with the RF/Analog/PMU design team to achieve competitive RFIC solution by advanced CMOS technology for WiFi6, Bluetooth/BLE and following WiFi7 application. Responsible for the design and development of high performance Frequency Synthesizer, including VCO, Divider, PFD, Charge Pump, Loop Filter, SDM etc.
Deeply research the top architecture of Integer/Fractional Frequency Synthesizer, modeling of the loop system to determine the design parameters of all sub-blocks, optimize the power consumption/layout area to meet the specifications of phase noise, spur and pulling
Verify and characterize Frequency Synthesizer with SoC/PHY/System teams. Analyze and debug chip issues and find solutions to fix, promote mass production
Track the evolution of RFIC design technology and provide technical support for system architecture implementation